As the number of circuits, particularly random access memory cells, on a semiconductor chip have increased, column and row redundant lines have been installed on the chip to enhance product yield. A chip that integrates various kinds of circuits including logic circuits having memory arrays embedded therein pose special problems for the circuit designer/tester who desires adequate testability of the embedded array since such chips have fewer input/output pins available to the circuit tester than is available in a chip having a stand alone memory.
To lower the cost of making memories by reducing testing expenses and improving memory yields, systems have been disclosed which are self testing and self repairing. One such system, sometimes known as an array built in self testing (ABIST) system, is taught in U.S. Pat. No. 4,939,694, issued on Jul. 3, 1990, which uses substitute address tables and error correction code (ECC) techniques for correcting errors found in the memory cells. Another ABIST system, disclosed in European Patent No. 0 242 854, published on Oct. 28, 1987, replaces defective memory cells of a semiconductor memory with spare memory cells using an associative memory. A further ABIST system is disclosed in U.S. patent application entitled "Built-In Self Test for Integrated Circuits" and having Ser. No. 07/576646, filed on Aug. 30, 1990, by E. L. Hedberg et al, now U.S. Pat. No. 5,173,906 wherein one dimensional failed address registers are used to store word addresses of defective cells of a memory array, i.e., redundant lines are used which extend in only one dimension.
To further improve memory chip yields, testing systems have been disclosed for testing chips having a memory matrix or array and spare or redundant columns and rows of memory elements to be used for repair of the matrix or array under test. One such tester is disclosed in U.S. Pat. No. 4,460,997, issued on Jul. 17, 1984, wherein defective cells detected or flagged when scanning in one direction, e.g., along a row, during test, are masked when scanning in the other direction, e.g., along a column, so as not to be counted as a defective cell twice. In commonly assigned U.S. Pat. No. 4,751,656, issued on Jun. 14, 1988, there is disclosed a method for choosing replacement lines in a two dimensionally redundant array wherein if the number of cell failures along a row exceeds the number of redundant columns, then that row is replaced with one of the redundant rows.